Capital Systems Modeler - Function Build List Consistency DRCs

There are particular design rule checks related to function build list consistency that you can run for a Capital Systems Modeler design.

Shared

signal/message with multiple ‘Out’ ports across designs in a buildlist

Identifies, within the selected build list, shared signals or messages that have multiple ‘Out’ ports defined. This check is available only if a build list has been defined in the project.

Messages	Variables
Shared Signal {0} is connected to multiple ports with direction ''Out''	{0} - Signal name
Shared Message {0} is connected to multiple ports with direction ''Out''	{0} - Message name

Shared

signal/message with no 'In' ports across designs in buildlist

Identifies, within the selected build list, shared signals or messages that have no ‘In’ ports defined. This check is available only if a build list has been defined in the project.

Messages	Variables
Shared Signal {0} is not connected to any ports with direction ''In''	{0} - Signal name
Shared Message {0} is not connected to any ports with direction ''In''	{0} - Message name

Shared

signal/message with no 'Out' ports across designs in buildlist

Identifies, within the selected build list, shared signals or messages that have no ‘Out’ ports defined. This check is available only if a build list has been defined in the project.

Messages	Variables
Shared Signal {0} is not connected to any ports with direction ''Out''	{0} - Signal name
Shared Message {0} is not connected to any ports with direction ''Out''	{0} - Message name

Parent Topic:

Design Rule Check Descriptions for Capital Systems Modeler

Capital Systems Modeler User Guide, 2512.2606

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