Wiring
Top-Level
Debugging Process for Synthesis
You can follow a particular process to debug wiring synthesis results. The process has a common start and then splits into three different processes: no synthesis required, no route available, and no synthesis solution.
Figure 304: Top-Level Debugging Process for Synthesis
Further details are available for the following debugging processes.
No Synthesis Required Debugging Process
The following diagram shows the process.
Figure 305: No Synthesis Required Debugging Process
No Route Available Debugging Process
The following diagram shows the process.
Figure 306: No Route Available Debugging Process
No Synthesis Solution Debugging Process
The following diagram shows the process.
Figure 307: No Synthesis Solution Debugging Process
Parent Topic:
Wiring
Related Topics
- Wiring Synthesis Output Troubleshooting
Capital Systems Integrator User Guide, 2512.2606
Unpublished work. © 2026 Siemens
Source: https://docs.sw.siemens.com/en-US/doc/861057055/202511026.capital_si_user/id7f314108-25e8-484f-9719-6732a49c629b · retrieved 2026-07-18