Unexpected Option Expression on a Generated Wire

Symptom: You observe an unexpected option expression on a wire generated during wiring synthesis.

Solution

This requires you to perform some investigation to determine why the wire has been assigned the option expression. To do this, you need to investigate all of the connectivity for that wire and its source signal:

1. Set all harness levels active to see all generated wires. Ensure that the whole signal is routed as you may need to investigate all of the generated wires for the signal and not just one wire.

2. Identify all the wires that carry this signal and: Identify the option expressions on the individual wires. If they have different option expressions, try to identify why they have the expressions that they do.

Identify multi-terms and splices to which the wires are connected. Identify whether there are any rules that apply to these objects, particularly regarding options.

3. Determine the option expression assigned to the source signal (net) in Capital Logic Designer. The wire should have that option expression within its own option expression.

4. Determine the option expression assigned to the connected pins/devices for the signal in Capital Logic Designer. The system passes options defined for those objects to any wires generated for the signal.

5. Consider any variant placement of connectors. When connectors are variantly placed, they are given another option expression that would also affect the option expression generated for connecting wires.

6. Consider any options assigned to bundles. These also affect the option expression for any wires that pass through them.

Parent Topic:

Troubleshooting Wiring Synthesis

Capital Systems Integrator User Guide, 2512.2606

Unpublished work. © 2026 Siemens