Wiring

Merge of Logical Multicores in Wiring Synthesis

A number of Capital features enable you to identify separeately designed nets as representing the same signal. These features include equivalence sets, combined devices in Capital Systems Integrator and the Equipotential attribute on pins in Capital Logic Designer. In each case, the individual nets are merged so that they represent a single signal in Capital Systems Integrator.

The system merges multicores along with the nets so that it can synthesize physical multicores. Not all of the logical nets need to be in a logical multicore. However, for those that are, the logical multicores must meet the following conditions:

For hierarchical (or nested multicores), each level of the multicore must be identical and meet the other constraints in this list.
The multicores must be the same type (that is, the indicator type must be the same).
The number and type of conductors in each multicore must be identical. This means, for example, if one multicore contains three nets and a shield, all the other multicores must contain three nets and a shield.
The resulting merged logical multicore must also match the number and type of conductors in each of the original multicores. This means that all the conductors in each multicore must be equivalenced to a conductor in the other multicore(s).
Attributes and properties on the multicores do not need to be the same. However, the systems considers them merged in the same way that attributes and properties on normal signals are merged. This means that, if there is a conflict, the resulting merged multicore act as if it does not have that particular attribute or property. This could effect the behavior of constraints.

If the multicores cannot be combined (that is, they do not have equivalent structures), the signals are combined but synthesis routes these signals as normal signals and does not put the wiring into a multicore. An error message displays on the Synthesis tab of the Output Window.

If previously combined multicores are modified in the associated logical diagrams so that their structures no longer match, the Sync tab in the Output Window displays a notification message but no wiring is removed from the combined multicore.

Parent Topic:

Wiring