Capital Schematic Generator for Systems Integrator > Topology Led Diagram

Generating

a Topology-Led Wiring Diagram

You can generate a single Capital Logic Designer wiring diagram based on the wiring information and bundle layout from the Capital Systems Integrator design. The wires follow the routes of the bundles in the Capital Systems Integrator design.

See Translation of Objects When Generating Topology Led Diagrams for more information about how Capital Schematic Generator for Systems Integrator generates these diagrams.

Prerequisites

You must have synthesized wiring in the Capital Systems Integrator design. See Synthesizing Wiring.

Procedure

Right-click the Capital Systems Integrator design in the Project Browser Window and choose Generate Wiring Diagram; the Generate Wiring Diagram Dialog Box dialog box displays.
From the drop-down list at the top of the dialog box, choose Generate Topology Led Diagram.
On the Design tab, specify the following for the generated design:Name

Revision

Release Level

Style Set

Parent Folder

On the Options tab (with “Generate Topology Led Diagram” selected), specify the following options for the diagram generation:Use Logic Diagram Grid Spacing

Use Refined Connectors

Minimum Wire Spacing

Click the Filter tab. Here you specify whether you want the generated diagrams to include wiring for particular vehicle configurations or harness levels (see Vehicle Configurations versus Harness Levels for some guidance). If you want to...

Do the following:

Use vehicle configurations

Do not select “Ignore configurations and show all harness levels”. If you have defined vehicle configurations for the Capital Systems Integrator design, the Configuration field displays.

Select the vehicle configurations for which you want to generate the wiring diagram or diagrams. The generated wiring diagrams contain all objects that are active in at least one of the vehicle configurations.

In the Harness field, select the harnesses that you want to be rendered in the generated wiring diagrams.

Use harness levels

Select “Ignore configurations and show all harness levels”.

In the Harness field, select the harness levels that you want to be rendered in the generated wiring diagrams.

The selection of particular harnesses or harness levels means that Capital Schematic Generator for Systems Integrator renders the following in the generated diagrams: Conductors, connectors, multicores and splices that are active in the selected configurations (if enabled) and that belong to the selected harnesses or harness levels.

Devices (and their pins) that are active in the selected configurations (if enabled), that are not integral to a harness and that are connected to at least one of the selected harnesses or harness levels.

Devices (and their pins) that are active in the selected configurations (if enabled) and that are integral to the selected harnesses or harness levels.

The Design field lists the Capital Logic Designer designs that are associated with the topological design. You can restrict the objects that are rendered in the generated wiring diagram by selecting particular associated designs. By default, all designs are selected.By selecting particular designs, you restrict the objects that are rendered in the generated diagrams to the following: Devices (and their pins) that are active in the selected configurations or harness levels and that have functional sources in the selected Capital Logic Designer designs

Wires and splices that are active in the selected configurations or harness levels and that belong to the signals that have functional sources in the selected Capital Logic Designer designs. This includes signals that represent net equivalence sets with at least one functional source in the selected functional designs.

Multicores that include at least one conductor that is active in the selected configurations or harness levels and that belong to the signals that have functional sources in the selected Capital Logic Designer designs.

Shields that are active in the selected configurations or harness levels, belong to the signals that have functional sources in the selected Capital Logic Designer designs and that connect to multicores rendered in the generated diagrams.

Connector pins attached to the conductors that are rendered in the generated diagrams.

Connectors whose pins are rendered in the generated diagrams.

Connector pins of the rendered connectors that have mated connector pins rendered in the generated diagram.

Backshells and backshell terminations.

Click OK.

Results

The new design and appropriate number of diagrams are generated and added to the Project Browser Tree for Capital Logic Designer.
One diagram is opened automatically in a diagram window.
The system generates an Wiring Diagram report in HTML format and saves it in a WiringDiagramReports sub-directory in your Capital temp directory. It has a name in the following format: CAVAI_Report_date_time.html. See Wiring Diagram Report for details about the report.

Parent Topic:

Topology Led Diagram