Example of Merging and Not Merging Splices in a Junction Connector Slot

You can use a Use device pin properties to define slot splice connectivity in prototype designs project preference to specify how wiring synthesis handles multiple splices in a prototype junction connector. That is, does synthesis result in a single merged splice in the junction connector or separate, distinct splices. This example demonstrates both outcomes.

See Project Preferences for Capital Systems Integrator Designs in the Capital Common Functions User Guide for more information about the project preferences available for Capital Systems Integrator.

In this example, there are several sensors, all connected to a common ground in Capital Wiring Integrator.

Figure 257: Merging versus Not Merging Splices – Capital Wiring Integrator Diagram

When wiring synthesis was first run for this, it resulted in a few splices that connected everything together.

Figure 258: Merging versus Not Merging Splices – Synthesis Run with Splices (Visualized Wiring)

You decide to optimize the manufacturing of these harnesses by implementing these splices in a junction connector. You can do this by implementing a prototype. This is the prototype in Capital Logic Designer.

Figure 259: Merging versus Not Merging Splices – Prototype Design in Capital Logic Designer

There is a junction connector in the middle of the prototype and all connectivity goes into it. The physical components have some shorting together of these cavities to maintain connectivity.

The following constraint is set on the Capital Wiring Integrator design to use the prototype for signal SNS-WHLSPD:

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Use wiring from SNS-WHLSPD:1 in configuration <all> for Signal Name = SNS-WHLSPD

Without the Use device pin properties to define slot splice connectivity in prototype designs preference selected, wiring synthesis for signal SNS-WHLSPD produces a solution that looks correct from the point of view of the wiring.

Figure 260: Merging versus Not Merging Splices – Synthesis Result with Preference Not Selected (Visualized Wiring)

Other than the layout of the wires, it is the same as the prototype, so the signal looks fine.

However, if you view the signal map of this junction connector, you can see that it has a single slot splice, so everything is shorted together.

Figure 261: Merging versus Not Merging Splices – Junction Connector Signal Map: One Merged Splice

In terms of connectivity, this works. However, it causes problems if you want to move one of the splices out and implement it as a bundle splice, with the others in the junction connector.

If you select the project preference and run wiring synthesis for signal SNS-WHLSPD, it produces this solution:

Figure 262: Merging versus Not Merging Splices – Synthesis Result with Preference Selected (Visualized Wiring)

It looks identical to the solution without the preference selected, but the junction connector’s signal map now shows that you have distinct splices.

Figure 263: Merging versus Not Merging Splices – Junction Connector Signal Map: Distinct Splices

That means, if you want to do an architectural study to determine whether it is more efficient to move one of these splices out, you can select one of them and move it as you would any other slot splice. You can do that quickly and efficiently, without having to implement any manual workarounds that could inadvertently cause errors in your wiring.

Note

The properties used when doing this (vizDeviceName, vizDevicePinName, vizDeviceDetails) are present on the device pins themselves, and these properties are automatically generated when you visualise the wiring for a signal, and save it as a prototype design. You can edit them in the prototype design if you want to change the specifics of mappings.

See Internal Device Properties in Wiring Views for more information about those properties.

Parent Topic:

Prototype Wiring

Capital Systems Integrator User Guide, 2512.2606

Unpublished work. © 2026 Siemens