Wires (Capital Wiring

Integrator)

The source wires from associated Capital Logic Designer designs are listed on the Wiring Browser. After these wires have been routed along the bundles in the topology diagram, they are displayed under the Routed > Unassigned node in the Design Browser or, if grouped into signals, under the Routed > Signals node.

The wires from the associated Capital Logic Designer designs are automatically routed along the bundles in the topology design when the devices that they connect have been placed in slots.

The real-world length of the wires is calculated using the Physical Scale of the topology diagram and is specified as the value of the Wire Length attribute on the Edit Properties: Wire Dialog Box. You can back annotate this length to the source wires in the Capital Logic Designer designs. If you have performed actions that changed bundle lengths, you may need to update the wire lengths before back annotating them.

• Constraining the Routing of Wires

• Using the Routing Assistant to Identify the Possible Routes for One or More Unrouted Wires

• Using the Routing Assistant to Identify Unrouted Wires

• Routing Assistant Behavior for Different Combinations of Conductors

• Reporting on All Unrouted Wires That Could Pass Through an Inline Connector

• Viewing the Attributes and Properties of a Wire

• Updating Wire Lengths

• Annotating Topology Wire Lengths and Harness Attributes Back to Logical Design Objects

Parent Topic:

Capital Wiring Integrator

Capital Logic Designer User Guide, 2512

Unpublished work. © 2025 Siemens