Detailed Descriptions of Wiring Synthesis Output

Wiring synthesis generates and routes wires in particular ways for specific scenarios.

Synthesis of Jumper Wires

If two device pins that are connected by a net conductor in a Capital Logic Designer schematic are placed in the same topological slot, each internal pin has its own cavity. When wiring is synthesized, these two cavities can be connected by a jumper wire. When you select the signal or wire in the Design Browser (Design tab) after wiring is synthesized, the jumper wire is highlighted in the diagram as an arc shape on the side of the slot.

Figure 206: Jumper Wire

Synthesis of Multicores

Where signals in Capital Logic Designer are grouped into a multicore, one or more physical multicores are created in Capital Systems Integrator when you synthesize wiring:

• The signals in a multicore are routed along the same bundles as far as possible and physical multicores are created in each harness where more than one wire is synthesized.

• If the multicore in Capital Logic Designer has a shield, a shield conductor is created for each physical multicore.

• Where the shield is unconnected in Capital Logic Designer, a cut-end splice is created in Capital Systems Integrator and positioned close to the end of the physical multicore to provide shielding over as much of the multicore as possible. You can control the offset of the cut-end from a connector using “Minimum Splice Separation” constraints.

• Where the shield is connected to a device in Capital Logic Designer (and where the multicore connects to an inline connector), Capital Systems Integrator synthesizes either a pigtail wire and splice or connects it directly to the connector cavity or backshell. You can control the actual implementation using constraints (see Overview of Rules and Constraints).

• After wiring synthesis, you can edit the shield termination. See Modifying a Shield Termination for more information.

Synthesis of Complex Multicores

In Capital Systems Integrator, a multicore is treated as a single cable containing exactly the same number of wires as defined in the associated Capital Logic Designer design.

During synthesis of a complex multicore, the implications of this are:

• If one or more of the signals follow a particular path (for example, through an inline), all the signals follow this path.

• Network synthesis supports networks that are embedded within another multicore.

• Whenever one or more of the signals in the multicore need to be spliced in order to connect to a device, all of the wires in the multicore are spliced.

• Where not all signals connect to a device, a constraint (Termination of single ended wires/shields) is applied to connectors to control whether synthesis creates dangling wires / shields that terminate on cut-end splices close to the device’s connector. These cut-end splices are supported when design data is passed to other Capital applications. If the wires are not created, the main multicore is still spliced (that is, with two wire splices).

If the logical multicore has a library part number assigned, it is not assigned to multicores containing fewer conductors.

• Sometimes, a signal within a multicore connects to more than one cavity at the same device connector. These additional connections result in a single splice in the appropriate signal’s wire and then two (or more) wires connected to the various connector pins. These additional wires are not included in a multicore.

• Although a multicore which terminates at multiple connectors normally needs to be cut and spliced, in some cases it is possible to terminate the innercores at multiple connectors without cutting. For example, if the connectors are close together, it may be possible to untwist the multi-core. You can apply a constraint (Maximum multicore takeout) to bundles to control the maximum length of untwist. In the case where the innercore (or shield) of a multicore is spliced with a 1:1 (two wire) splice, this constraint is applied. If the length of wire from the splice to the connector is less than the length specified by this constraint, the splice is not created.

In the case that a shield has a pigtail, the length used to check against this constraint is the total length from the 1:1 splice to the connector (that is, the length of the shield and pigtail wire added together).

This constraint has no effect on pigtail splices (used to terminate shields).

• The synthesized cut-end splices are supported when wiring is exported or imported.

Examples of Multicore Routing

The following are simple examples of multicore routing from wiring synthesis.

In each case:

• The top image is a logical system design from Capital Logic Designer.

• The middle image is the associated topological design from Capital Systems Integrator.

• The bottom image is the resulting wiring design generated using Capital Schematic Generator for Systems Integrator. Example 1: Twisted Pair

This example contains a simple twisted pair and shows that two physical multicores are created because of the inline.

Example 2: Single-ended Shielded Multicore

This example contains a single-ended shielded multicore and shows how pigtails are synthesized at the inline and left-hand device. This could also show that a cut-end splice is created near DEV4 (this would need to be shown in Capital Systems Integrator because it is not shown in a wiring diagram).

Example 3: Multiple-ended Twisted Pair

This example contains a special case of a multiple-ended twisted pair (typically used for networks). Note that there is only one multicore in the logical schematic, but four physical multicores are created.

Network Wiring Synthesis

For detailed descriptions of the information required by wiring synthesis for handling backbone or daisy-chained networks, and how it generates them, see either:

• Backbone Networks in Wiring Synthesis

• Daisy-chained Networks in Wiring Synthesis

Parent Topic:

Wiring

Capital Systems Integrator User Guide, 2512.2606

Unpublished work. © 2026 Siemens