Multicores

The multicores from associated Capital Logic Designer designs are listed with their innercore wires on the Wiring Browser.

Before being routed, multicores are listed under the Unrouted node in the Design Browser (Capital Wiring Integrator), with their innercore wires listed below them. Unrouted multicores from overbraids are listed under the Unrouted node also.

If an object under the Unrouted node is partially routed, an orange circular arrow displays on its icon (for example, ).

After these wires have been routed along the bundles in the topology diagram, the routed innercore wires are displayed under the Routed > Unassigned node in the Design Browser (Capital Wiring Integrator) or, if grouped into Signals, under the Routed > Signals node.

The innercore wires from the associated Capital Logic Designer designs are automatically routed along the bundles in the topology design when the devices that they connect have been placed in slots.

The real-world length of the innercore wires is calculated using the Physical Scale of the topology diagram and is specified as the value of the Wire Length attribute on the Edit Properties: Wire Dialog Box. You can back annotate this length to the source wires in the Capital Logic Designer designs.

• Viewing the Attributes and Properties of a Multicore

• Using the Routing Assistant to Identify the Possible Routes for One or More Unrouted Multicores

• Recommended Paths for Partially Routed Multicores

• Routing of Multicores with Pigtail Wires

• Failure Cases for Split Multicore

Parent Topic:

Capital Wiring Integrator

Capital Logic Designer User Guide, 2512

Unpublished work. © 2025 Siemens