Rules and Constraints > Usage Examples for Rules and Constraints in Capital Systems Integrator

Rules to Add Properties

and Attributes to Wires, Splices and Multicores During Wiring Synthesis

You can set rules on objects so that specific properties and attributes are added to wires, splices or multicores during wiring synthesis. The properties and attributes can have fixed values or a value derived from an attribute or property of the signal (or functional multicore) from which the wire or splice or multicore is being routed.

There are three constraints that you can use for this (see Overview of Rules and Constraints for more information about the general use of rules and constraints):

Wire Specification Allows you to specify that a wire should have an attribute or property with a fixed value or a value derived from an attribute or property of the signal from which the wire is being routed. For example: Wire Spec: Wirecolor is ValueOf(color) where Signal matches Name=.* In this case, a wire has a Wirecolor attribute with a value derived from the value of the color property of the signal.
Splice Specification Allows you to specify that a splice should have an attribute or property with a fixed value or a value derived from an attribute or property of the signal from which the splice is being routed. For example: Splice Spec: Type is ValueOf(splicetype) where Signal matches Name=.* In this case, a splice has a Type attribute with a value derived from the value of the splicetype property of the signal.
Multicore Specification Allows you to specify that a topological multicore should have an attribute or property with a fixed value or a value derived from an attribute or property of the functional multicore from which the topological multicore is being routed. For example: Multicore Spec: Sheath Type is ValueOf(type) where Multicore matches Name=.* In this case, a topological multicore has a Sheath Type attribute with a value derived from the value of the type property of the functional multicore.

The following design rule checks are available to check for wires/splices/multicores that violate any applicable specification constraints:

Wires violating specification rules
Splice that breaks specification rule
Multicore that breaks specification rules

See Running Design Rule Checks Manually for more information about running design checks.

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Usage Examples for Rules and Constraints in Capital Systems Integrator