Notes on DRCs

for Aerospace Modular Connectors

The design rule check (DRC) Incompatible Mated Connector accommodates the multi-mating of modular inserts to a single connector with regard to aerospace modular connectors. The following examples demonstrate how this works in practice.

If a connector is mated to an aerospace modular connector or its child inserts, this check compares the number of pins / cavities of the source connector to total number of pins / cavities of the mated aerospace modular connector or mated child inserts.

For example, if a device side connector having 12 pins is mated to both pins of an aerospace modular connector, and all 5 pins of both of its child connectors, it is a valid mating.

If the source connector is completely mated to all the pins / cavities of a parent aerospace modular connector or one or more of the child modular inserts, it is a valid mating.

For instance, if a device side connector having 7 pins is mated to both pins of an aerospace parent modular connector, and all 5 pins of one of its child modular inserts, it is a valid mating.

Similarly, if a device side connector having 5 pins is mated to all 5 pins of a modular insert of an aerospace modular connector, it is a valid mating.

The updated Incompatible mated connector messages trigger only when a connector is mated to an aero‑modular connector (to the parent modular connector or one or more of the child modular inserts):

For instance, if a device side connector having 7 pins is mated to only 1 pin of an aerospace parent modular connector and all 5 pins of one of its child modular inserts, it is an invalid mating.

Instead of reporting two different lines for this erroneous case, the new message uses a single line as shown below:

For other matings not involving aero-modular connectors, error messages display in separate lines instead of a single line.

See also “Capital Logic Designer - Library Consistency DRCs” in the Capital Design Tools - Common Functions User Guide.

Parent Topic:

Modular Connectors

Capital Logic Designer User Guide, 2512

Unpublished work. © 2025 Siemens