Prototype Wiring

You can use wiring designs from Capital Logic Designer as prototype (template) wiring for signals and multicores when you synthesize wiring in Capital Systems Integrator. If a signal (or multicore) has some part of the implementation that is difficult for wiring synthesis to achieve using rules and constraints, you can specify just that part of the signal with a prototype. The wires from the prototype are copied and wiring synthesis runs for the rest of the signal automatically using constraints. This ensures flexibility when you make changes to either the logical systems or the harness topology.

You use wiring designs that you have created manually in Capital Logic Designer or have created by saving visualized wiring views from Capital Systems Integrator (the system saves these wiring views as Capital Logic Designer designs).

You set a constraint against the Capital Systems Integrator design to specify that the system uses prototype wiring from a particular Capital Logic Designer design when synthesizing particular signals or multicores. The constraint allows you to specify which configurations use the prototype wiring.

Caution

Each prototype design must match exactly one signal or one combined signal or one logical multicore or one combined multicore. Prototype designs should not have a colon ':' in their names.

Prototype wiring does not support a prototype design that contains multiple non-multicore signals or multiple logical multicores. In this scenario, you must create multiple prototypes, one for each logical multicore.

The system applies the constraints in any synthesis run. That means, the copied, prototype wiring always forms part of a synthesis result. If synthesis identifies the prototype connectivity as invalid, it generates an error.

If you remove a prototype constraint from a design, the system unlinks the wiring generated using the prototype from the prototype so that incremental synthesis runs re-use the existing wiring as much as possible. This behavior applies only when no prototype constraint exists for a generated wire. If a prototype constraint exists but the system cannot match a related wire to any wire in the prototype design, then an incremental synthesis run deletes the previously generated wire.

Note

In some cases, when wire option expressions are recalculated, the system may report variant wiring generated by the prototypes as redundant. This is reported in the Synthesis tab of the Output Window at the bottom of the application.

Some things to consider when creating prototype wiring designs in Capital Logic Designer:

• You do not have to add slot connectors to the prototype wiring design. This makes the prototype more flexible since you can use it even when the slot signal map changes. This video shows a simple example of prototype wiring. This video shows a complex example.

            Note 
                This complex example shows an approach where you use separate Prototype
                    Wiring constraints and separate prototype designs for different
                    configurations. You can now use a single, composite prototype wiring design
                    for multiple configurations. See Example of Using a Single Prototype Wiring Design for Multiple Configurations.
  

• If a device is variantly placed, you may need to add a connector to the prototype wiring design to differentiate the various placements.

• Wiring synthesis will ignore the names of connectors, pins, wires, and splices in the prototype design if they are default names. Capital Systems Integrator will name them using standard naming functionality. This can be helpful, for example, for specifying a connector for variant placement, but not specifying the exact pins (again to allow the signal map to change independently of the prototype). You can also use this technique for specifying inline connectors, but not the exact cavity (allowing you to define preferred signals in Capital Systems Integrator).

• When synthesis uses a prototype it matches the wires in the prototype against any existing wires in the Capital Systems Integrator design. This matching uses device, connector and cavity names in the prototype. However, in some cases where multiple wires connect between the same connectors, and the cavities in the prototype use default names, the matching can be ambiguous resulting in existing wires being deleted and re-created. You can avoid this by specifying the exact connector cavity name in the prototype.

• When synthesis uses prototypes for wires, it uses a hierarchical approach to match device pins and connector cavities from the prototypes with those in the Capital Systems Integrator design. This helps to ensure accurate connections even in cases with multiple devices in a slot. The system follows this hierarchy for cavity selection:
  Fixed cavity names When a wire in a prototype goes to a connector cavity with a fixed name, synthesis only attempts to route the wire directly to the specified cavity.
  
  
  Unfixed cavities with visualization properties When a wire in a prototype goes to a connector cavity with an unfixed name, synthesis checks the connected device pin for visualization properties vizDeviceName, vizDevicePinName, and vizDeviceDetails. It routes the wire to the device pin defined in those properties, via the connector cavity mapped to that device pin. In the case of multiple device pins being defined in these properties, synthesis must make at least one match.
  
  
  Unfixed cavities without properties When a wire in a prototype goes to a connector cavity with an unfixed name and the connected device pin has no visualization properties, synthesis falls back to the existing cavity selection algorithm. In this case synthesis considers a number of variables such as object names and other wires present at connector cavities, to make a selection.

• If you have multiple prototype designs for a single signal, you can re-use a splice between them by giving it the same (not default) name.

• The matching with regard to generalized (refined) connectors and specialized connectors is as follows: It is possible in a prototype to specify either a generalized (refined) connector or a specialized connector.

If a prototype connector has a name that matches both a generalized connector and one of its specialized connectors, then the assumption is that the user meant to specify the specialized connector.

If a generalized connector is matched, then the cavity names in the prototype are ignored. Instead, the system looks at the specialized connectors and uses preferred signals, and so on, to identify the appropriate cavity to use.

If a specialized connector is matched, then the cavity names in the prototype are used (if specified).

This video shows an example of using prototype wiring related to a multicore.

When applying the prototype wiring, the system does the following with regards to properties and attributes on the copied wires:

• Copies properties from the wiring to the synthesized wiring.

• Copies attributes from the wiring to the synthesized wiring (unless they have the default value). Note that you can set non-copied attributes by using other constraints in Capital Systems Integrator. However, copied attributes override any values from Capital Systems Integrator constraints.

• Copies wire and splice names where you have overridden the default name. Note that it does not copy default names and Capital Systems Integrator sets the names of such objects using standard naming rules.

After specifying prototype wiring constraints to a design, you can run an Applied Prototype Wiring report that lists all prototype constraints that have been assigned in the currently open design. See Applied Prototypes Report.

You can also run “Invalid prototype constraint” and “Wiring does not match prototype” design rule checks to identify any prototype wiring constraints that are invalid and to identify where synthesized wiring does not match prototype wiring. See “Capital Systems Integrator - Design Assistant DRCs” in the Capital Design Tools - Common Functions User Guide.

• Example of Using a Single Prototype Wiring Design for Multiple Configurations

• Generating a Wiring View of a Synthesized Signal or Multicore

• Optimized Pin and Multicore Indicator Positioning

• Building Up a Wiring View of Synthesized Signals or Multicores

• Usage Example of Building Up a Wiring View

• Usage Example of Storing a Wiring View

• Visualizing Wiring for Internal Slot Connectivity

• Specifying Prototype Wiring Constraints

• Refined Connector Attributes and Properties in Wiring Views

• Internal Device Properties in Wiring Views

• Placement Option Expression in Wiring Views

• Prototype Wiring Error and Warning Messages

• Example of Merging and Not Merging Splices in a Junction Connector Slot

Parent Topic:

Wiring

Capital Systems Integrator User Guide, 2512.2606

Unpublished work. © 2026 Siemens