Capital Schematic Generator for Logic Designer

Specifying Layout Styling When Generating Diagrams

When using Capital Schematic Generator for Logic Designer to generate diagrams, you can use the Layout Styling tab to specify the default styling for the layout of the diagrams.

Diagram flow — Specify whether you want the layout of the components, pins, and conductors on the diagram to flow horizontally (left to right), or vertically (bottom to top).

Figure 77: Horizontal Flow

Figure 78: Vertical Flow

Enable connector flow — Select to have pins only on the sides of devices and connectors that follow the direction of the Diagram flow. That is, on the top and bottom sides in a vertical flow, and on the left and right sides in a horizontal flow. This restricts the connector placement to the sides of devices following the flow.

Clear to have pins on all sides of devices and connectors, and therefore do not want to restrict connector placement on devices.

Figure 79: With Connector Flow

Figure 80: Without Connector Flow

Note

Harness-side connectors become shared if they have multiple instances on the generated diagram as a result of the flow.

Enable Tree Layout — Select to create diagrams using a tree layout that reflects the specified Diagram flow direction. Clear to create diagrams using a graph representation that reduces the overlapping of connectivity and bends in conductors. The following considerations are relevant to this type of layout:

Generated diagrams do not have a flow.
Pins are not always evenly distributed.
Conductors may have 90 degree bends.

Figure 81: With tree layout

Figure 82: Without Tree Layout

Enable device stretching — Select to stretch devices on the generated diagram to reduce net jogs, and the crossover of conductors. The device height and width exceeds nominal pin grid spacing. Otherwise, do not select.

Figure 83: With Device Stretching

Figure 84: Without Device Stretching

Optimize parallel placements of tree devices — Many devices can directly associate to a single device. Select to graphically represent associations by aligning the devices vertically or horizontally. This is considered a one-to-many connection. An example is an ABS module, and its sensors.

Enable connector splitting by proximity — Select to split the graphical representation of harness connectors around the devices to which they belong, if it reduces net jogs, and conductor crossover. Otherwise, do not select.

Figure 85: With Connector Splitting

Figure 86: Without Connector Splitting

Enable inline splitting — Select to split the graphical orientation of inline connectors around devices.

Auto select border to fit — Select to automatically select a suitable border to fit the design.

Connect Indicators with Daisy Chain — The layout of diagrams generated using Capital Schematic Generator for Logic Designer can become complex as separate shield terminations are created for each multicore on the design. If the design includes numerous shielded multicores, you can select Connect Indicators with Daisy Chain to simplify the layout of generated diagrams.

Figure 87: Without Daisy Chain

Figure 88: With Daisy Chain

Use device symbols — Select to retain and display device symbols on the generated diagrams using the associated symbols in the symbol library. Clear to create parameterized symbols, which you can replace later.

Enables the following options that control how differences between device symbols in the design and the library symbols are generated:

With exact pin name match only — Select to ensure symbols are only generated when the device pin names and count match the library symbol exactly. If pin names or counts do not match, the details are displayed in the Output window.
Remove properties not on symbol — Select to remove any properties from the device symbol that are not on the library symbol. Clear to retain the properties on the device symbol.
Copy attribute/property values from symbol — Select to copy the values for any matching attribute and property names from the library symbol to the generated symbol. Clear to retain the values from the device symbol. Default.

Preserve attribute/property text

          Select to retain the attribute and property visibility settings
              on the device symbol. Clear to copy the visibility settings from the library
              symbol.

Preserve pin names — Select to retain the pin names on the device symbol. Clear to copy the pin names from the library symbol. Default. Figure 89: Without Use Device Symbols

Figure 90: With Use Device Symbols
Plugin support (Custom Layout Settings) — For logical designs, symbol retention works in both default Capital and custom plugin flows. For functional designs, symbol retention is only available when using custom plugins developed with the Capital APIs. The default functional design plugin will always generate parameterized devices regardless of symbol settings. Logical designs:

Default plugin — Core Capital layout with full symbol retention

Custom plugin — Custom layout rules with symbol retention

Functional designs:

Default plugin — Symbol retention not supported

Custom plugin — Symbol retention when created using Capital APIs

For more information about developing and using extensibility plugins, see the PluginDevelopment.pdf file located in the doc\plugin folder of your Capital software installation.

Minimum conductor length — Specify the minimum distance in grid spaces that can exist between any two devices, connectors, or splices that are connected by a conductor. If a greater length is specified, more white space is displayed between objects on the diagram.

Minimum device width — Specify the minimum width in grid spaces for devices on the diagram.

Tip

To ensure the pin decoration text does not spill over the device box use a font size of 0.4 inch/10 mm or smaller. Alternatively, select Increase device box width to accommodate pin decoration to automatically determine the width of devices.

Increase device box width to accommodate pin decoration — Used to avoid manually resizing the width of devices and improve the readability of generated diagrams.

Select to automatically increase the graphical width of devices to accommodate pin decorations that may extend beyond the device bounding box or overlap with adjacent pin decorations. Clear to use the “Minimum device width” value to determine the width of devices.

Figure 91: With Increase Device Box Width

Figure 92: Without Increase Device Box Width

Parent Topic:

Capital Schematic Generator for Logic Designer