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Wiring

Synthesis Output Troubleshooting

When wiring synthesis has run, the Synthesis tab in the output window at the bottom of the application reports on the synthesis actions and signals that have failed to route. For a failed signal, you can click the Details link to view the reasons why it failed to route. When you click the link, the details display on the Signal Details tab in the Output Window.

You can click Save detailed failure report to access the Select Output File dialog box that enables you to save a report detailing failed signals and the reasons why they failed to route. You can save the report in CSV (comma-separated values) or HTML format.

Each pane also has a pop-up menu, accessible with a right mouse button click, that contains text manipulation commands (Select All, Copy, and Clear).

Note

You can also use the Design Assistant to calculate the routed state of signals (signal states) or can generate a wiring view of a synthesized signal (see Generating a Wiring View of a Synthesized Signal or Multicore). However, the Synthesis tab remains the primary source of messages to understand synthesis failure.

After wiring synthesis, you can switch to a Synthesis Analyzer mode that helps you to investigate why a signal has not routed in particular configurations. In this mode, you view diagram objects related only to that signal in a particular configuration. This means, you can clearly see where the signal has stopped and investigate that location. See Switching to Synthesis Analyzer Mode for a Signal and Synthesis Analyzer Mode Overview Videos.

What Causes a Signal Not to Synthesize

Wiring?

There are various possible causes of a signal not synthesizing.

System thinks no synthesis is required
No route is available
No synthesis solution is possible
Option dependencies are too complex

System Thinks No Synthesis Is Required

This occurs when there are fewer than two active device pins for the signal. This situation is typically identified when you expect some wiring but find it is missing. This is not considered an error and therefore does not normally result in warning or error messages on the Synthesis tab in the Output Window.

Causes

Unmapped Device Pins You must map all device pins to a slot connector cavity. For example: Figure 295: Signal Map Showing Unmapped Pin
Inactive Device Pins A pin must be active in at least one harness level. If it is not, this can be caused by: Missing option on harness family You can use the Design Assistant to investigate this. See Reporting on Missing or Inconsistent Options Promoted to Harnesses.

Conflict between effective device pin option expression and harness levels This normally requires you to manually check the option expressions on device pins and harness levels. The Design Assistant reports if a pin is never active when you calculate the routed state of signals. The conflict may also be on another harness family. You can use an Options and Levels report to identify harness families to check. See Creating an Options and Levels Report.

Messages Displayed when System Thinks No Synthesis Is Required

The application can display various messages.

Synthesis Tab in Output Window	Design Assistant Messages
None (not a synthesis error)	Harness is missing option
	Option not referenced in any levels
	Unmapped in slot
	Connects to cavity which is never active

Steps to Identify Issues

Use the Design Assistant to run design rule checks to identify options not referenced by any harness levels and options that should be promoted from placed devices. See Running Design Rule Checks in the Design Assistant.
Use the Design Assistant to run a signal status check on all configurations to identify unmapped device pins as well as pins that are never active. See Calculating the Routed State of Signals.
If a pin is never active, calculate its effective option expression by combining expressions from the device pin, the device, the net and variant placement of the device (if any). Examine harness level definitions to ensure this option expression is supported by at least one harness level. Note It may be necessary to consider other harness family level definitions. For example, if the effective option expression of the device pin is (LHD && ABS), you need to ensure that every harness family that supports both these options has at least one harness level that has them both active.

No Route Is Available

In this case, the system cannot find an available path between all active device pins. Typically, this is reported during synthesis, but requires investigation to determine the exact cause.

Causes

All of these causes are reported on the Synthesis tab of the Output Window when synthesis is run.

No physical path between harnesses For example: Figure 296: No Physical Path Between Harnesses This can also be caused by a multi-harness slot with the correct signal mapping.
Path broken by optioned bundles You can debug this using graphical filtering. For example: Figure 297: Path Broken by Optioned Bundles
Path broken by inlines with no available cavities This can only occur if you have assigned part numbers to the inline pair and can be caused by incorrect Preferred Signal settings in the Signal Map for the inline pair. Figure 298: Path Broken by Inlines with no Available Cavities
Path broken by routing constraints Figure 299: Path Broken by Routing Constraints

Messages Displayed when No Route Is Available

The system can display various messages.

Synthesis Tab in Output Window	Design Assistant Messages
Harness is not physically connected	Partially routed due to unconnected groups
Disconnect due to no available cavities
Disconnect due to option expression
Disconnect due to routing/splice constraint

Steps to Identify Issues

View the Synthesis tab of the Output Window at the bottom of the application to identify the possible issues. Note that you could also use the Design Assistant to run a signal status report (see Calculating the Routed State of Signals).
If a harness is not physically connected: Check slots and inlines that appear to provide a connection.

Check for errors in signal mapping in multi-harness slots.

Check for disconnects in the topology. You can identify disconnects using the Unterminated Bundle design rule check or by unexpected harness names in the browser list.

If several disconnects are identified, some of them may be expected. Set all harness levels as active and then select the signal in the Design Browser (Design tab) so that it is highlighted in the diagram window. Identify slots that need to be connected together and identify the expected routing paths. If the signal is partially routed, you can use the groups of wiring reported by the Design Assistant to identify where there is a gap in the expected route.
Work through any disconnects reported on the Synthesis tab of the Output Window and identify any that appear on the expected routing path.

No Synthesis Solution Is Possible

In this case, routing paths exist between the active device pins but the required wiring could not be synthesized.

Causes

Consider the following:

Are multi-terms allowed? If multi-terms are disallowed (as below), the only mechanism to join wiring together is splices. Figure 300: Constraint Preventing Multi-terms
Are splices allowed? If splices are disallowed (as below), the only mechanism to join wiring together is multi-terms. Note that splices can only be created along the path of a signal’s wires. Figure 301: Constraints Preventing Splices
Are bundles long enough to support the required number of splices? Splice separation rules can stop a splice being created, especially when bundles are short or have many takeouts. Note that a rule for “Maximum wires per splice” can result in more splices needing extra space. Figure 302: Constraints Preventing Splices Due to Bundle Length

Messages Displayed when No Synthesis Solution Is Possible

The system can display various messages.

Synthesis Tab in Output Window	Design Assistant Messages
Constraints could not be met	Partially routed due to unconnected groups

Steps to Identify Issues

Set all harness levels as active and then select the signal in the Design Browser (Design tab) so that it is highlighted in the diagram window. View the connected slots.
Look for a probable route and select a bundle where a splice might be expected. If the signal is partially routed, you probably want to look at the bundles that already have wires created. In order to finish the route, one or more of these wires needs to be spliced or multi-termed.
View the bundle’s properties and view the Rules tab. Click the Show Inherited button.

Look for wires per multi-term and wires per splice constraints.

If there are constraints that completely restrict splice and multi-term creation, consider whether any splices/multi-terms are possible anywhere in the design.

Look at the Rules and Constraints report for the diagram and determine whether these constraints apply to the whole design or whether there are some places in the design where the system can create splices/multi-terms. See Creating an Applied Constraints Report. If a splice cannot be created in any of the harnesses joining the slots on a signal, synthesis probably fails (because it only considers adding splices along the path of an existing wire).

If the constraints restricting splice and multi-term creation appear correct and you can create splices in the design, repeat the above looking for splice separation constraints. Consider the splice separation that is required and therefore the minimum length of a bundle required to create a splice. If all the bundles in the area where a splice is required are too short, synthesis fails.

Option

Dependencies Are Too Complex

In this case, synthesis fails due to the complexity of options that have been defined.

Causes

Wiring synthesis generates abstract configurations for each signal. When the option relationships in the project are very complex (that is, there are lots of inclusive and exclusive relationships) the process of generating abstract configurations becomes more complex (because it needs to consider a large number of options). Processing this large number of options can cause the process to be very slow and memory intensive.

Messages Displayed when Option Dependencies Are Too Complex

Synthesis Tab in Output Window	Design Assistant Messages
Error: Cannot generate configurations for signal on vehicle model	None

Steps to Address Issue

Navigate to the config/clientprops.xml editor in your installation, and open the file in an editor.
Find the parameter, ensure it is uncommented, and increase the optionconstraintlimit value.

Caution

This value can be increased to a maximum of 100000000. Values above this, or smaller than the default of 1500000 will be ignored.

If you increase this limit, you may have other issues with memory usage and performance, so you should consider reviewing the interdependencies in the options, rather than just increasing the value.

Parent Topic:

Wiring