Terminal Bars, Holes and Relays

Terminal Bar

Design Flow

You can use holes and slot circuit functionality in Capital Systems Integrator to implement terminal bars.

Create logical diagrams in Capital Logic Designer. You do not create terminal blocks or terminal bars at this stage.
Create the topology in Capital Systems Integrator. When doing this, define slots as junction boxes to represent terminal bars. See Overview of Junction Box Slots.
Add holes to the junction box slots. See Adding a Hole to a Slot.
Connect bundles to the holes. Bundles/harnesses that terminate at holes do not have a harness-side connector. Unlike slot connectors: Holes cannot have bundle fanouts so the Refine Connector functionality is not available on a hole.

Holes cannot be marked Integral to Harness.

Any wires connecting to slots through holes are considered to terminate internally on the splice or device placed in that slot. You can route signals through a junction box slot. This creates internal splices between two hole connections. You can visualize these internal splices as follows: Figure 171: Internal Splices Multiple connections to the same placed functional device pin are also represented as an internal splice.

Place functional devices in the slots with holes. This applies to diodes or other devices in junction box slots to be manufactured with the terminal bar. See Placement of a Device or Ground Device in a Slot.
Synthesize wiring to create splices in the junction boxes. See Composite Wiring Synthesis. You can route wires to holes and terminate the wires at them. Any wire terminating at a hole is a poke home.

Hole connections are never multi-termed (there is no connector pin or cavity on which to terminate). Instead, wires on the same signal are internally-spliced so that routes are completed.

Internal splices display in the Design Browser (Design tab) when they are connected to wires routed via a hole.

It is possible for an internal splice to connect signals between two different holes but it is not possible for internal splices to connect signals between holes and slot connector cavities.

In order to force splice creation inside the junction box slot, you would apply rules to other slots, harnesses or the design that prohibit splices and multi-terms.

Signal Map You can use the Signal Map dialog box to alter signal mapping to holes in junction box slots. The behavior of the Signal Map dialog box is slightly different when a slot has holes.

A hole contains 'hole connections' but you do not see or manipulate these directly. You determine only the hole for each signal. You do not select which cavity is connected to a given signal.

However, you could add additional holes (without a cavity) or slot connectors (with a cavity) to the slot as mappings for a given signal.

Internal splices are shown explicitly in the Signal Map dialog box when the wires in the splice are connected via a hole.

Use Generate Slot Circuit functionality to output a graphical representation of the slot. You could either print this, export the design or use Capital E/E Reporter to generate a custom report. Slot Circuits The Generate Slot Circuit functionality can be used with holes. See Slot Circuit for more information about slot circuits. When a signal is mapped to a hole connection, then a wire (with a name based on the external wire at that connection) is used to represent the connectivity from the appropriate internal splice or placed device. When signals are mapped to more than one hole connection (that is, an internal splice), the corresponding wires are spliced together using standard Capital Logic Designer parameterized splices (that is, 1-pin splices with no symbol). In the case of holes, it is not possible to generate a wire that passes through the slot without being connected to a splice. There is no limit on the number of wires connected to an internal splice. Wires are also displayed connected to parameterized devices that represent the logical devices, such as diodes, that are placed in the slot. Example of Generating a Slot Circuit: You have a slot in Capital Systems Integrator. Figure 172: Slot in Capital Systems Integrator If you used a connector instead of the hole, generating a slot circuit would create a connector with net conductors indicating the internal short: Figure 173: Connector with Net Conductors With the hole, the wires are shown spliced together without a connector because the wires connect directly to the internal splice. Figure 174: Hole with Wires Spliced
You use your own process (outside of Capital) to create definitions of terminal bars and terminal blocks which you can input back into Capital Systems Integrator. These definitions must be in XML format and be structured as in the following example. In this example, the terminal bar definition represents a single terminal bar with two terminal blocks. The first block TB1 has three pins, including the connection for the bar conductor, and one for mating to a terminal block connector. All three pins are shorted internally, so TB1 is essentially a splice. The second block TB2 has one pin only. The jumper connects one pin from each terminal block.

Import the external definition of terminal bars and terminal blocks. The system stores this information with the junction box slot for future reporting and consistency checking. See Importing Terminal Bar Definitions for more information.
Run the “Inconsistent terminal bar” design rule check that reports any inconsistencies in the internal connectivity between the previously imported terminal bar definition and the slot itself (that is, the placed devices and the signal map). See Running Design Rule Checks Manually for more information about running design rule checks. The “Inconsistent terminal bar” check validates that wires connected together by slot-internal splices created by wiring synthesis correspond to the wires connected together by terminal bar data. Terminal bar data includes terminal block internal connectivity, jumpers between terminal bar pins and the conductive bar itself. This verifies that changes to the signal map, changes to placement data or changes to wiring in Capital Systems Integrator have not invalidated the terminal bar definition and that the terminal bar definition itself corresponds to the slot's model of internal connectivity. This design rule check also verifies that the connectivity of components embedded in the terminal blocks corresponds to the slot-internal connectivity of the corresponding functional devices placed in the slot.
The terminal bar data is now persisted and is passed on to other Capital applications that use the data from Capital Systems Integrator. Note Capital Schematic Generator for Systems Integrator does not support holes and terminal bars. You can use Enterprise Reporter to report on terminal bars.

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Terminal Bars, Holes and Relays