Capital Wiring Integrator > Bundles

Constraining

the Placement of Splices on a Bundle

Yu can use the Minimum Splice Separation and Place Splice/s on Bundle by Attribute/Property constraints to control the creation and placement of splices on a bundle. The Minimum Splice Separation constraint enables you to specify the minimum distance that there must be between a splice and a connector, bundle device, takeout, or another splice. The Place Splice/s on Bundle by Attribute/Property constraint enables you to specify whether splices with a particular property or attribute are placed on a bundle.

See Splices in Capital Wiring Integrator for how Capital Wiring Integrator places splices when no constraints are specified.

Note

You can bundle constraints into rules that you can set on objects. See Rules and Constraints to create rules.

Rules and constraints adhere to hierarchies. That means, if they are set on an object, child objects inherit them. For example, you can set constraints for a diagram so that they are inherited by all objects on the diagram (in this case, all slots and connectors). See Setting Constraints for an Entire Topology Diagram.

Procedure

Select a bundle or a parent object of bundles (a harness):Press the space bar and enter Properties.

Right-click and select Properties.

Double-click the bundle in the Diagram window.

The Edit Properties dialog box is displayed. To apply this constraint to objects on the diagram, see Setting Constraints for an Entire Topology Diagram.

Click the Rules tab.
Click the Add Constraint button.The Constraint Selection dialog box is displayed.
Choose Minimum Splice Separation or Place Splice/s on Bundle by Attribute/Property and click OK.The constraint is added to the Edit Properties dialog box.
Edit the constraint as required.
To use both constraints on the bundle, repeat Steps 4 to 6 for the other constraint.
Click OK.

Results

The constraint is applied when Capital Logic Designer designs are associated with the topology diagram and when updated data from the Capital Logic Designer design is synchronized with the topology design.

Parent Topic:

Bundles