Options Tab (with Custom Partitioned Diagrams Selected)

To access: Right-click a platform design in the Project Browser Window and choose Generate Wiring Diagram. The Options tab is displayed in the Generate Wiring Diagram Dialog Box.

Certain fields are available on the Options tab when Custom Partitioned Diagrams is selected at the top of the Generate Wiring Diagram dialog box.

Objects

Field	Description
Partitioning Property	Select the user-defined property that exists on the functional devices and pins in the associated Capital Logic Designer designs to control the partitioning of the generated wiring designs.
Slot Internal Connectivity	Select one of the following: None - Select this for the wiring diagrams to include any slot internal connectivity. In this case, device names and pin names are generated from the names of the slots in which they are located in the Capital Systems Integrator design. Minimum - Select this for the wiring diagrams to include slot internal connectivity only if it is required to display slot-external connectivity correctly. In this case, device names and pin names are taken from the functional designs in Capital Logic Designer. All - Select this for the wiring diagrams to include all slot internal connectivity. In this case, device names and pin names are taken from the functional designs in Capital Logic Designer. Filter - Select this for the wiring diagrams to include slot internal connectivity only for specific slots. When you first select this, the Filter Selection Criteria dialog box displays automatically. You can access the dialog box again by clicking the ellipsis (…) button. See Specifying Filters for Generation of Slot Internal Connectivity. See Generation of Slot Connectivity in Partitioned Diagrams for a detailed description of how slot internal connectivity is generated in these different modes. Caution When you use prototype designs for diagram generation, the current generation must use the same Slot Internal Connectivity settings as were used for the prototypes.
Exclude slot graphics	This is available when you select All, Minimum, or Filter for 'Slot Internal Connectivity' and is relevant to a work flow that uses Capital E/E Publisher. If you clear this, internal connections and objects are created, and the external facing pins are mated to a virtual slot object. The connectors then all mate to that device. This causes problems if you want to perform ‘click and sprout’ (where connectivity is automatically rendered) on the internal connectivity in Capital E/E Publisher. This is because the slot can have many pins and ‘click and sprout’ shows a large device that can make the generated diagram hard to read. Select this to produce diagrams with no slot devices. This means, you can select all the internal devices in Capital E/E Publisher without having to navigate through the slot device, and you are able to perform 'click and sprout' on that internal connectivity. Therefore, generated designs are more easily analyzed within Capital E/E Publisher. Service technicians and end-of-line engineers can easily trace the internal connections of a slot, such as the fuses in a power distribution board, and this helps them to identify faults quicker.
Diagram Flow	Select how inline connectors are orientated in the generated diagrams. Default Inline connectors can be orientated both horizontally (pins going left to right) and vertically (pins going bottom to top), depending on how they are currently orientated in diagrams. Horizontal All inline connectors are placed for a horizontal flow, that is, pins going left to right. Vertical All inline connectors are placed for a vertical flow, that is, pins going bottom to top. Your choice here depends on the diagram flow you used when creating the functional diagrams in Capital Logic Designer. That is, if you created a functional diagram following a horizontal flow (where devices have connectors on the left and right, and nets follow horizontal paths), then you select Horizontal here so that the system places inline connectors, devices and splices in a horizontal manner. If your functional diagrams follow a vertical flow (where devices have connectors on the top and bottom, and nets follow vertical paths), you select Vertical here. If a functional net is horizontal, and you select Vertical here, inline connectors, devices, and splices will appear horizontally in the generated diagram because there is no vertical net to guide a vertical placement of these. The same is true for ported nets. That is, if a ported net is vertical in the functional diagram, and you select Vertical here, then inline connectors, devices, and splices will appear vertically in the generated diagram. If the ported net is horizontal in the functional diagram, and you select Horizontal here, then the objects are horizontal.
Always Add Ground Paths	Select this for the sotware to add ground paths on every wiring diagram as required. Ground paths include wires, inline pairs, splice segments and the ground terminal itself.
Distribute Splices	Select this to distribute splice connectivity across the generated wiring diagrams. You can break splice symbols and distribute them across each sheet to provide a continuous path on every sheet. This is an alternative to a conservative view in which the entire splice is represented on a single sheet. For an example of a generated wiring diagram with and without distributed splices, see Wiring Diagram with and without Distribute Splices Selected.
Pin and Device Name Retention	Displayed only with a Slot Internal Connectivity setting of None. In some cases, the pin names in the generated designs do not match those in the original Capital Logic Designer functional designs. Select this to display the original pin names on the generated diagram when this is the case. In the generated design: The original pin name is stored as a property on the pin and is set as visible. The generated name of the pin is not set as visible so is not displayed on the diagram. The functional source name for a device is retained only if it is the only device in a slot. The functional source name for a pin is retained only if it is the only pin representing a cavity, and it represents a single cavity (that is, a one to one mapping). Clear this to display the generated pin names.
Utilize Combined Devices	Displayed only with a Slot Internal Connectivity setting of Minimum or All. In Capital Systems Integrator, you can combine devices to create a single entity and signal. Select this for the devices to remain combined in the functionally-partitioned diagrams. Clear this for the devices to be separate in the functionally partitioned diagrams, and for multiple paths to be generated to each shared device pin. This is ideal for combining ground symbols. You do not necessarily know that they are combined until you create the physical representation of them. At that time, you can combine them in Capital Systems Integrator and use this option to recognize that change.
Property Retention	Displayed only with a Slot Internal Connectivity setting of None. In some cases, there is a conflict between the values of the properties on the pins or devices in the functional source diagrams. This can be the case if you have mapped multiple functional pins to one pin in Capital Systems Integrator or if you have placed multiple functional devices in one slot in Capital Systems Integrator. If you do not select this, the properties of the functional source pins and devices are not copied onto the pins and devices in the generated diagrams. Select this to store all the conflicting property values in separate properties on the objects in the generated diagrams. Any properties that are modified are visible in the Edit Properties dialog box for the object in the generated diagram but are not visible on the diagram itself. In the case of property conflicts where the values are different, the system resolves them by appending the name of the property owner. For example: Dev1 has the properties: Prop1 with the value VALUE_1 Dev_Prop with the value VALUE_1 Prop with the value VALUE Dev2 has the properties: Prop2 with the value VALUE_1 Dev_Prop with the value VALUE2 Prop with the value VALUE When the properties are merged on a generated device, the properties are as follows: Prop1 with the value VALUE_1 Prop2 with the value VALUE_1 Dev_Prop_Dev1 with the value VALUE_1 Dev_Prop_Dev2 with the value VALUE_2 Prop with the value VALUE If the properties of a pin need to have conflicts resolved, the new properties on the generated diagram have names in the form .
Merge Combined Device Properties	Displayed only with a Slot Internal Connectivity setting of Minimum or All. It is enabled only if Utilize Combined Devices is checked. Select this option for combined devices in the functionally partitioned diagrams to inherit properties and attributes from all functional source devices. The device names are prefixed with the functional device names if there is a naming conflict. Clear this for combined devices to inherit the properties and attributes from one functional source device that is selected randomly but deterministically.
Hide Unconnected Pins and Connector Cavities	Select this to hide unconnected pins and connector cavities on objects in the generated diagrams. Clear this to display unconnected pins in the generated diagrams.
Use Refined Connectors	Clear this for the generated wiring diagrams to have one wiring connector for each slot, interface, or inline connector. Select this for the generated wiring diagrams to have one wiring connector for each refined connector. See Connector Refinement and Signal Mapping for an overview of refining connectors. Note An appropriate error message displays for cases where refinement was not honored.
Multicore Indicator Offset	Specify the offset in pin grids between multicore indicators and the end of the multicore. For example:
Wire spacing	When multiple, parallel-running wires use the same guided layout from the functional (system) designs, there may be results where wire decorations overlap. Specify the distance (measured in pin grids) between the newly generated wires which are following the same guided layout. This is also applicable to the spacing of other wires. For example: Wire spacing = 1 Wire spacing = 10
Minimum Wire Length	Specify the minimum length (in pin grids) of a wire section for wires derived from single-ended functional nets and/or newly added wires. Any wire section will be this length or longer. For example, if you specify 10 pin grids, each wire section will be at least 10 pin grids. If the length of the single-ended net in the functional design is more than the specified minimum wire length, the software uses the functional net length. If the length of the single-ended net in the functional design is less than the minimum wire length you specify here, then the software uses the specified minimum wire length.

Parent Topic:

Generate Wiring Diagram Dialog Box - Options Tab

Capital Systems Integrator User Guide, 2512.2606

Unpublished work. © 2026 Siemens