Backbone Networks in Wiring

Synthesis

Through the use of object attributes and constraints, you enable wiring synthesis to support backbone networks.

You can watch the following video for an example of defining a backbone network in Capital Logic Designer and Capital Systems Integrator:

Backbone networks (for example, LIN, CAN, FlexRay) are typically implemented as a linear bus created using multiple twisted pairs which are spliced together. A typical physical implementation is as follows:

Figure 266: Network Wiring Example Implementation

Each network has a number of rules that govern its structure, depending on the type of bus. You can categorize these rules as follows:

Figure 267: Network Wiring Structure Rules

• Connections are made by a twisted pair multicore or a single wire.

• Multi-terminations are not allowed (splices are used where more than two devices are connected).

• The ends of the bus are connected to devices containing resistor terminations. These two devices are separated by the longest wire length in the network.

• The overall length of the bus between the ends (L) has a maximum length.

• The multicore stubs that tie devices to the bus (l) have a minimum and maximum length (a stub is defined as a twisted pair or single wire connecting a device to a splice on the bus).

• There is a minimum distance (d) between stubs (splices).

• When an optional device is not attached to the network, the stub for that device should not appear on the harness and bypass wires take the place of the splice.

Before wiring synthesis can generate wiring for a backbone network, you must specify object attributes or constraints that provide synthesis with information about the following:

• Maximum length of network and length of stubs

• Pins at end of network

Maximum Length of Network and Length of Stubs

You can set a “Network specification” constraint on the Capital Systems Integrator design. It identifies a multicore as being a backbone network and also controls the maximum length that a backbone network can have in the wiring generated by wiring synthesis for signals or multicores with a particular attribute.

For example, for signals with Name attributes starting with CAN (such as CAN1 and CAN2), you could specify a maximum length of 10000.0, stubs of lengths between 2000.0 and 4000.0, and a minimum distance of 1000.0 between stubs:

Network specification has max length = 10000.0 min stub length = 2000.0 max stub length = 4000.0 stub distance = 1000.0 where logical Signal Name = CAN.*

Pins

at End of Network

You must also consider which pins are at the end of the network.

There are two ways of doing this:

• In Capital Logic Designer: Specify a Pin Type attribute for pins. You can set a Pin Type attribute of IxOTerminated on the pins at the ends of the network. Note You can also set a Pin Type attribute of IxO on pins on network stubs in Capital Logic Designer.

• In Capital Systems Integrator (before running wiring synthesis): Add “Network termination” constraints to appropriate objects. You can add this constraint to a cavity, slot connector, interface connector, hole, slot, or diagram. It cannot be applied to an inline or its cavities. It enables wiring synthesis to set pins as IxOTerminated when a multicore or signal going to that pin has a particular property or attribute value. For example: You could set pins as IxOTerminated when signals with names starting with CAN (such as CAN1 and CAN2) go to them. Figure 268: Network Termination Constraint

Synthesis

of Backbone Network

After you have defined the necessary attributes or constraints, wiring synthesis then does the following for backbone networks:

• Applies the Network specification constraint to network signals and identifies them by using the following rules: If a “Network Specification” constraint matches a top-level multicore, all signals in that multicore and its children belong to the same network, regardless of whether the signals also match other “Network Specification” constraints. If any of the signals match a different constraint, a warning is generated. Only top-level multicores are matched against the constraint.

If a multicore does not match the constraint but all of the signals within the multicore match a “Network Specification” constraint, they are treated as a network. A warning is generated if not all of the signals match or if some match another “Network Specification” constraint with different values. In this case, none of the signals are routed as a network. Note If a shielded multicore matches a “Network Specification” constraint, a warning is generated. The multicore wiring is synthesized as for a network and the shield is added as for any other multicore.

A signal that is not in a multicore but that matches a “Network Specification” constraint is routed as a single core network.

• If a network signal does not have exactly two terminated cavities, it is not routed and wiring synthesis generates an error. If the values specified for stubs in the “Network Specification” constraint cannot be met for a signal, it is not routed. However, if the max length for the network cannot be met for a signal, it is still routed. You can identify this situation by running the design rule check for “Network wiring that breaks specified limit” after wiring synthesis.

• Only splices connect stubs to the network (never multi-terminations or direct connections to other stubs).

• Splices adhere to the “Network Specification” constraint with regard to the length of a wire from an unterminated device and the distance between stub splices. A splice also adheres to any “Minimum Splice Separation” constraint.

• During the routing of a signal for a non-terminated device, a splice adheres to the “Network Specification” constraint. That means, it may be pulled back along the stub bundle or pushed on to the mainline bundle.

• When optional devices are not active, bypass wiring is used. Wiring synthesis adds the bypass wires to the multicore if all of the active wires have been bypassed.

Backbone

Network Starting and Ending at Same Device

Backbone networks usually start at one device and end at another. However, there is a use-case where the network starts and ends at the same device. The path of the network backbone forms a loop, starting and terminating at the same device. Network stubs are spliced off this backbone for each network node. For example, here you can see a loop from pins PIN1 and PIN2 to pins PIN3 and PIN4 on the Terminated Device:

Figure 269: Backbone Network in a Loop

The logical system design for this example backbone network is as follows:

Figure 270: Logical System Design for Backbone Network in a Loop

Note that both COND6 and COND9 connect to two pins on the terminated device. Wiring synthesis will generate two multicores connected to the device (as shown in the first figure). However, there is no information to help synthesis know whether it should connect a multicore to pins PIN1,PIN2 and PIN3,PIN4 or PIN1,PIN4 and PIN2,PIN3. All synthesis can identify is that there is a pair of nets connected to four pins.

You can tell synthesis which pins should be grouped together by assigning each pair of pins to a separate ‘network group’.

There are two ways of doing this:

• In Capital Logic Designer: Specify a Network Group attribute for pins in a network group. The value of the Network Group attribute on a pin indicates the network group to which that pin belongs. The value (which acts as a network group name) can be anything (for example “1” or “2”, “in” or “out”) but must be the same for the pins in a group. Capital Systems Integrator uses these values to identify network groups when synthesizing wiring. Below is an example where Capital Systems Integrator needs to know that the following pins are paired as network groups: CAN1H and CAN1L are a network group 1.

CAN2H and CAN2L are a network group 2.

Figure 271: Network Groups You therefore specify a Network Group attribute of 1 on pins CAN1H and CAN1L, and a Network Group attribute of 2 on CAN2H and CAN2L. Note Remember that the network groups can be named anything as long as the attribute value is the same for all pins in a group. 1 and 2 are just examples.

• In Capital Systems Integrator (before running wiring synthesis): Add “Daisy-chained network group” constraints to appropriate objects. You can add this constraint to any object from a pin upwards (pin, connector, slot, design). It specifies that a device pin or cavity matching a particular attribute value belongs to a particular network group. Using the same example again, you could set the following constraints: Figure 272: Network Group Constraints Wiring synthesis will recognize pins CAN1H and CAN1L on the device as network group 1, and recognize CAN2H and CAN2L as network group

Parent Topic:

Backbone and Daisy-chained Networks

Capital Systems Integrator User Guide, 2512.2606

Unpublished work. © 2026 Siemens