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Capital Wiring Integrator > Multicores

Using the Routing Assistant to Identify the Possible Routes for One or

More Unrouted Multicores

You can use the Routing Assistant to identify all possible, common routes for one or more unrouted multicores. Each stage of the route may or may not be complete in the associated Capital Logic Designer designs. The Routing Assistant also displays details of viable and unviable routes, and where you must add an instance of an inline pair in the Capital Logic Designer designs to complete a route.

Restrictions and Limitations

  • When the ‘Enable multi-user editing of designs’ project preference is set to true for Capital Logic Designer designs, the Place Inline action is not permitted. See Multi-User

Access to Capital Logic Designer Designs for information about this project preference and multi-user access.

  • The viability of a route is determined using the following three factors:

    Available pins on the inline connector part number

    Available unrestricted pins on the shared inline connector

    Wire specification compatibility

    Note When checking wire specification compatibility, the system considers only the connector cavity definition. When checking available pins, the system also checks that a pin is available where a shield termination is required. Where there are multiple shields and not enough pins, no shields or pigtails are terminated. When termination of a shield fails due to insufficient space, this is due to the presence of wires, not devices.

  • The system evaluates viability with regard to the current path only. For example, if there are ten viable paths and you implement one of those, you will need to run Routing Assistant again because the viability of the remaining nine paths may change as a result.

  • The system considers a shared pin as consumed once it is used in a project. Therefore, it will not be included in viability calculations or the Place Inline action.

Prerequisites

Consider whether you want to use 'Pigtail usage by attribute/property' constraints. When placing inline connectors, the Routing Assistant uses pigtail wires to terminate shielded multicores at inline connectors by default. You can set a 'Pigtail usage by attribute/property' constraint on the topology design or on an inline half to control whether the Routing Assistant uses a pigtail, shield, or no termination for multicore shields for a shield signal with a particular attribute or property when placing an instance of an inline half. See Routing Assistant in the Standard Constraints for Capital Wiring Integrator topic.

Procedure

  1. Under the Unrouted node of the Design Browser (Capital

Wiring Integrator) or under the Designs node of the Wiring Browser, select one or more unrouted multicores for which you want to identify possible routes and either:

          Right-click and select Routing
              Assistant.

        

        
          Click the Show Routing
              Assistant button () in the Design Browser or Wiring
            Browser.

        

        
          Press the space bar and enter Route.

        

      

    
    
      Alternatively, if the Routing Assistant is already open, you can drag
        and drop multicores from a tab for a Capital Logic Designer design or a Capital Wiring
        Integrator design into the Routing Assistant. The multicores must exist in Capital
        Wiring Integrator and be unrouted. If a dragged multicore does not meet those criteria,
        a message is displayed in the Output window.

    
    
      Note 
        If part of a multicore is assigned to a harness already, the text
          partial is displayed next to it under the Unrouted node. A tool tip informs you to which bundle it is assigned. 

        The behavior of the Routing Assistant can vary depending on the
          combination of conductors that you selected and where you selected them, see Routing Assistant Behavior for Different Combinations of Conductors for more information.
  1. A progress bar indicates that the system is identifying the routes and it displays the common, unique routes for the multicores in the Routing Assistant tab in the Output Window. Note When you use the Routing Assistant for unrouted wires from a multicore that has some wires routed already, the Routing Assistant recommends a path to maintain consistency and minimize divergence. See Recommended Paths for Partially Routed Multicores.
    When you select a route in the Routes table so that the row is highlighted in blue, the To‑Do List table (on the right) displays the details for the stages of the selected route. See “Routing Assistant” for a detailed description of the information in this table. Figure 188: Route Selected in Routes Table (Routing Assistant)


    Note The routes displayed in the Routes table and To-Do List table have an icon to indicate whether they are viable and implemented: viable route not implemented , viable route implemented , unviable route that is not implemented , unviable route that is implemented . You can toggle whether the Routes Table displays only viable routes (the default) or both viable and unviable routes by clicking the button. The application remembers what you selected when you last used Routing Assistant. This toggle works in conjunction with the Show shortest route only filter so you can select to show just the shortest viable route.

  2. In the Routes table, select the Place column for the route that you want the multicores to follow; the To-Do List table displays the details for the stages of the selected route.

  3. For each stage of the route where a wire is displayed in red, you must add an instance of an inline connector to an associated Capital Logic Designer design so that the wire passes through it. To do this, click the Place Inline button (). If you click a wire cell in the To-Do List table, a tooltip displays additional information about it, including links to any instances of that object in the Capital Wiring Integrator diagram or in the associated Capital Logic Designer diagrams. You can click the link to jump to the Capital Logic Designer diagram where the instance of the inline connector is required. Figure 189: Wire Cell Tooltip (Routing Assistant)


    If you click a From or To connector cell in the To-Do List table, a tooltip displays an inline connector report that includes information about the connector (see Connector Details Dialog Box for descriptions of the fields). You can click the Show connector detail icon () at the top right of a connector cell tooltip to access the report. It reports on the unrouted wires present in the selected route through the inline connector. The report can be saved as a CSV file. Figure 190: Connector Cell Tooltip (Routing Assistant)


    When you click Place Inline, a Place Inline Pair dialog box warns you that you cannot undo this action. Note There are various cases in which the Place Inline action can fail. See Failure Cases for Place Inline.

  4. If there are more than one inline pair that you can place (because there are multiple inline connectors along the route in Capital Wiring Integrator), you choose the inline pair to place in the Place Inline Pair dialog box, and then click Place. The system places the inline pair in the appropriate Capital Logic Designer diagrams. A Manage Connections Dialog Box is displayed. It lists the pins on the inline connector instance and the multicores that are connected to them. If the inline halves in Capital Wiring Integrator had no part numbers, the Place Inline action creates pins in a logical fashion using default naming. If they had part numbers, it uses names from the library parts. Note If an inline connector is placed in a viable location, the system will intelligently map pins to the wire based on the wire specification. If the relevant Capital Logic Designer diagram is currently read-only, the Place Inline action attempts to acquire the lock on the design, places the inline, and then releases the lock.

  5. Use the Manage Connector dialog box to edit the pin to multicore connections as you require and click OK. Note The newly split mulitocre (that is, those from the routing assistant) display with an icon in the Manage Connector dialog box. This helps you to identify which are the new wires. To add multiple inline connectors, click the Refresh Wiring button () in the Design Browser after placing an inline connector, and then use the Routing Assistant again to place the next inline connector.

Results

  • The viability of routes is checked again and the icons in the Routing Assistant are updated accordingly.

  • When a stage of a route is completed for a wire in the Capital Logic Designer diagrams, the wire name in that To-Do List table row changes from red to black.

  • When a stage is complete for all wires following that route, the status column for it in the To-Do List table displays a tick ().

  • When all stages are complete for all wires following that route, the status column for the route in the Routes table displays a tick ().

  • If the system adds the inline connector to more than one design, it shares the inline connector automatically.

  • The system splits the inline connector on a diagram if there are more than four grid points between wires. Figure 191: Split Inline Connector

  • If the inline halves in the Capital Wiring Integrator diagram had a value specified for their Part Number property, the system looks for the part numbers in Capital Component Manager. If the part numbers exist, the system assigns the part numbers to the appropriate inline connectors when it creates them in the Capital Logic Designer designs.

  • If you place an inline in a multicore that is part of an overbraid, the action splits all of the wires in the multicore and creates a new multicore in addition to the existing one. Figure 192: Multicore Before Place Inline


    Figure 193: Multicores After Place Inline


    Note There are various cases in which the Split Multicore action can fail. See Failure Cases for Split Multicore.

Parent Topic:

Multicores

Related Topics

  • Routing Assistant Behavior for Different Combinations of Conductors

  • Recommended Paths for Partially Routed Multicores

Capital Logic Designer User Guide, 2512

Unpublished work. © 2025 Siemens

Source: https://docs.sw.siemens.com/en-US/doc/861057055/202410078.capital_ld_user/yta0928506902606 · retrieved 2026-07-18