Wiring

This section contains details of how to synthesize (generate) wiring and edit wires.

• Synthesizing Wiring

• Composite Wiring Synthesis

• Composite Wiring Synthesis Flows

• Modular Wiring Synthesis

• Abstract Bypass Wiring in Modular Wiring Synthesis

• Bypass Wiring for Combined Signals at a Splice

• Toggling the Visibility of Always Bypassed Wires

• Mixed Modular and Composite Synthesis Flow

• Non-composite Wiring Synthesis

• Deleting the Synthesized Wiring for all Signals

• Deleting the Synthesized Wiring for Selected Signals

• Deleting Obsolete Wiring for a Slot, Connector, or Signal

• Detailed Descriptions of Wiring Synthesis Output

• Running Modular or Composite Wiring Synthesis for Selected Signals

• Merge of Logical Multicores in Wiring Synthesis

• Synthesis Configuration

• Combine Identical Harness Levels

• Prototype Wiring

• Import of Carry-Over Wiring

• Backbone and Daisy-chained Networks

• Wire Editing in Capital Systems Integrator

• Combined Signals and Combined Wires

• Assigning Wire / Splice / Multicore Properties by Rules

• Splice Editing in Capital Systems Integrator

• Creating a Multicore

• Twisted Pairs and Pitch Tables

• Automatic Change of Multicore Type During Wiring Synthesis

• Updating Wire Lengths

• Modifying a Shield Termination

• Copying Wiring Across the Levels of a Harness

• Depopulating Wiring from Active Harness Levels

• Editing Ground Signals

• Exporting Wiring from a Capital Systems Integrator Design

• Importing Wiring into a Capital Systems Integrator Design

• Editing the Module Code for a Wire, Shield or Multicore

• Routed States of Signals

• Preserving Wiring during Topology Edits

• Editing the Topology in Preserve Wiring Mode

• Wiring Synthesis Output Troubleshooting

• Synthesis Analyzer Mode

• Top-Level Debugging Process for Synthesis

Capital Systems Integrator User Guide, 2512.2606

Unpublished work. © 2026 Siemens